This invention relates to a microcomputer for use in combination with a memory to process a sequence of instruction codes in a pipeline fashion. Although a sequence of data signals can be also processed in such a microcomputer, description will be mainly made about processing the instruction codes hereinunder because this invention is not directly concerned with processing the data signals.
In a conventional microcomputer of the type described, a bus control unit is coupled to a memory through a bus to access the memory and to thereby carry out a write-in or a readout operation of the instruction codes between the memory and the bus control unit. During the readout operation, each instruction code is successively sent from the bus control unit to an instruction code memorizing circuit to be memorized in the instruction code memorizing circuit and to be read as a readout instruction code. The readout instruction code is delivered as an execution instruction code from the instruction code memorizing circuit to an execution unit and is executed by the execution unit.
With this structure, each readout instruction code is read out of the memory during the readout operation to be sent from the bus control unit to the instruction code memorizing circuit as the execution instruction code prior to execution of the execution unit. Thus, each readout instruction code is prefetched from the memory to the bus control unit before execution of each readout instruction code. Under the circumstances, each execution instruction code is executed by the execution unit in a pipeline fashion independently of the readout and the write-in operations carried out in the bus control unit.
Herein, it is to be noted that the instruction codes specify either branch instruction codes or the other instruction codes which may be called ordinary instruction codes, such as data transfer instruction codes, arithmetic calculation instruction codes, etc. In addition, the branch instruction code is classified into a conditional branch instruction code and an unconditional branch instruction code.
When such a branch instruction code is required from the execution unit in the conventional microcomputer with a previously prefetched instruction code memorized in the instruction code memorizing circuit, such a previously prefetched instruction code should be rendered invalid or cancelled in the instruction code memorizing circuit. Thereafter, the branch instruction code must be read out of the memory and sent from the bus control unit to the execution unit through the instruction code memorizing circuit.
This shows that the occurrence of the branch instruction causes a disturbance of pipeline control and hinders high speed execution of the instructions.